RegViz: Visualize RSER Bitfield

Freescale Semiconductor /MKL82Z7 /QuadSPI0 /RSER

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Interpret as RSER

ABSEIE=0, DLPFIE=0, RBDIE=0, ILLINIE=0, IPGEIE=0, AITIE=0, TBFIE=0, TFIE=0, RBDDE=0, TBUIE=0, AIBSIE=0, ABOIE=0, TBFDE=0, IPAEIE=0, IUEIE=0, RBOIE=0, IPIEIE=0

Description

Interrupt and DMA Request Select and Enable Register

Fields

TFIE	Transaction Finished Interrupt Enable 0 (0): No TFF interrupt will be generated 1 (1): TFF interrupt will be generated
IPGEIE	IP Command Trigger during AHB Grant Error Interrupt Enable 0 (0): No IPGEF interrupt will be generated 1 (1): IPGEF interrupt will be generated
IPIEIE	IP Command Trigger during IP Access Error Interrupt Enable 0 (0): No IPIEF interrupt will be generated 1 (1): IPIEF interrupt will be generated
IPAEIE	IP Command Trigger during AHB Access Error Interrupt Enable 0 (0): No IPAEF interrupt will be generated 1 (1): IPAEF interrupt will be generated
IUEIE	IP Command Usage Error Interrupt Enable 0 (0): No IUEF interrupt will be generated 1 (1): IUEF interrupt will be generated
ABOIE	AHB Buffer Overflow Interrupt Enable 0 (0): No ABOF interrupt will be generated 1 (1): ABOF interrupt will be generated
AIBSIE	AHB Illegal Burst Size Interrupt Enable 0 (0): No AIBSEF interrupt will be generated 1 (1): AIBSEF interrupt will be generated
AITIE	AHB Illegal transaction interrupt enable. 0 (0): No AITEF interrupt will be generated 1 (1): AITEF interrupt will be generated
ABSEIE	AHB Sequence Error Interrupt Enable: Triggered by ABSEF flags of QSPI_FR 0 (0): No ABSEF interrupt will be generated 1 (1): ABSEF interrupt will be generated
RBDIE	RX Buffer Drain Interrupt Enable: Enables generation of IRQ requests for RX Buffer Drain 0 (0): No RBDF interrupt will be generated 1 (1): RBDF Interrupt will be generated
RBOIE	RX Buffer Overflow Interrupt Enable 0 (0): No RBOF interrupt will be generated 1 (1): RBOF interrupt will be generated
RBDDE	RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain 0 (0): No DMA request will be generated 1 (1): DMA request will be generated
ILLINIE	Illegal Instruction Error Interrupt Enable. Triggered by ILLINE flag in QSPI_FR 0 (0): No ILLINE interrupt will be generated 1 (1): ILLINE interrupt will be generated
TBFDE	TX Buffer Fill DMA Enable 0 (0): No DMA request will be generated 1 (1): DMA request will be generated
TBUIE	TX Buffer Underrun Interrupt Enable 0 (0): No TBUF interrupt will be generated 1 (1): TBUF interrupt will be generated
TBFIE	TX Buffer Fill Interrupt Enable 0 (0): No TBFF interrupt will be generated 1 (1): TBFF interrupt will be generated
DLPFIE	Data Learning Pattern Failure Interrupt enable . Triggered by DLPFF flag in QSPI_FR register 0 (0): No DLPFF interrupt will be generated 1 (1): DLPFF interrupt will be generated

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